New RISC-V hardware designs from 5G startup EdgeQ | GeekComparison

Today, 5G mobile startup EdgeQ announced the addition of two new members to its advisory board: former Qualcomm CEO Paul Jacobs and former Qualcomm CTO Matt Grob. Their mission is to halve the Total Cost of Ownership (TCO) of 5G mobile base stations by leveraging and expanding open hardware RISC-V designs.

Traditionally, Radio Access Network (RAN) devices tend to have a closed design and be deeply owned. Such closed stacks generally cannot be upgraded to accommodate new protocols and usage scenarios – for example, a radio unit or distributed unit designed for 4G networks typically needs to be replaced in its entirety to serve 5G devices. .

In contrast, vendors can implement their own OpenRAN solutions, which generally implement fewer features in hardware and more in software that runs on traditional operating systems such as Linux. But properly implementing such an O-RAN requires a very deep protocol expertise to do it right, and it is usually extremely energy consuming and expensive to maintain once completed.

EdgeQ’s approach is to effectively split the difference between traditional closed silicon approaches and expensive O-RAN. EdgeQ has licensed a reference RISC-V CPU design and added new hardware instructions to speed up the computationally expensive vector math operations required to handle 4G and 5G communications and signal processing.

Adil Kidwai, VP and Head of Product Management at EdgeQ, says the new instructions are not the standard RVV vector math extension. Kidwai describes EdgeQ’s ISA extension as a set of “custom vector instructions to achieve high performance at low power consumption for 5G infrastructure solutions.”

According to EdgeQ CEO Vinay Ravuri, the company’s innovative approach reduces power consumption from 100W (using a Xeon-based solution) to 10W, with nearly all of the work done in EdgeQ’s SoC itself. In a cell tower’s DU, this could mean separate hardware for machine learning acceleration, timer sync, FEC acceleration, front and midhaul transport, and L1 processing are all condensed into the single EdgeQ SoC — and, again according to EdgeQ, the TCO by up to 50 percent.

Since the vector mathematical instructions required for 5G signal processing and communication are largely the same as for machine learning tasks, excess processing power in EdgeQ’s CPU can be allocated to local ML processing. According to Ravuri, mobile communication is a huge workload, with the CPU being idle most of its time. The cores of the RISC-V CPU can be partitioned directly, with some allocated to 4G/5G and some to ML, or workloads can be distributed on a Quality of Service (QoS) managed basis.

We think the most important part of EdgeQ’s design is flexibility. By providing customers with true C/C++ access to its RISC-V SoC, EdgeQ enables not only innovation, but also future adaptability. Such a system can be upgraded on site to accommodate future protocol upgrades, where less flexible systems should get a “forklift upgrade” – meaning you lift the old one, slide the new one in and then throw the old one away for recycling.

EdgeQ is far from the only company in this general space — hard drive vendors Western Digital and Seagate have each started implementing RISC-V designs into some emerging hardware designs, and they’ve done it for similar reasons. . We hope this expansion of RISC-V designs into previously closed silicon spaces continues, especially in the consumer Wi-Fi world, where greater programmability could reduce the rise of e-waste as protocols change.

List image by EdgeQ

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