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This slide from IBM’s preview announcement provides more details about the new process design.
IBM
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This wafer contains hundreds of simple prototype chips built on the new 2 nm process at IBM’s research plant in Albany.
IBM
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Transmission electron microscopy gives us a detail of the triple-stack GAA (Gate-All-Around) transistors in the new process.
IBM
On Thursday, IBM announced a breakthrough in integrated circuit design: the world’s first 2 nanometer process. IBM says the new process can produce CPUs that can deliver either 45 percent higher performance or 75 percent lower power consumption than modern 7nm designs.
If you’ve been following recent processor news, you’re probably aware that Intel’s current desktop processors still run at 14nm as the company struggles to complete a migration to 10nm — and that its rivals run on much smaller processes, with the smallest production chips Apple’s new M1 processors at 5nm. What’s less clear is what that means in the first place.
Originally, process size referred to the literal two-dimensional size of a transistor on the wafer itself, but modern 3D chip fabrication processes have turned that into a hash. Foundries still refer to a process size in nanometers, but it is a “2D equivalent metric” only loosely linked to reality, and its true meaning varies from manufacturer to manufacturer.
To get a better idea of how IBM’s new 2nm process stacks up, let’s take a look at the transistor densities, with information on Wikichip’s manufacturing process and information on the IBM process courtesy of Dr. Ian Cutress of Anandtech. Cutress had IBM translate “the size of a fingernail” — enough area to pack 50 billion transistors using the new process into 150 square millimeters.
| Manufacturer | Example | Process Size: | Peak Transistor Density (millions/sq mm) |
| Intel | Cypress Cove (desktop) CPUs | 14 nm | 45 |
| Intel | Willow Cove (laptop) CPUs | 10 nm | 100 |
| AMD (TSMC) | Zen 3 CPUs | 7 nm | 91 |
| Apple (TSMC) | M1 CPUs | 5 nm | 171 |
| Apple (TSMC) | next-gen Apple CPUs, circa 2022 | 3 nm | ~ 292 (estimated) |
| IBM | May 6 prototype IC | 2 nm | 333 |
As you can see from the chart above, the simple “nanometer” metric varies quite strenuously from one foundry to another – Intel’s processes in particular have a much higher transistor density than is implied by the “process size” metric, with its 10nm Willow Cove CPUs roughly match 7nm parts coming from TSMC’s foundries. (TSMC builds processors for AMD, Apple, and other leading customers.)
While IBM claims the new process could “quadruple cell phone battery life, leaving users only needing to charge their devices every four days,” it’s far too early to attribute any concrete power and performance metrics. of chips designed for the new process. Comparing transistor densities with existing processes also seems to take the wind out of IBM’s sails. Comparing the new design to TSMC 7nm is well and good, but TSMC’s 5nm process is already in production and the 3nm process, which has a very similar transistor density, is on track for production status next year.
We have no announcements of actual products in development for the new process yet. However, IBM currently has partnerships with both Samsung and Intel, who may be able to integrate this process into their own future production.
List image by IBM