AMD triples Zen 3 CPU cache with 3D stacking technology | GeekComparison

Yesterday at Computex 2021, AMD CEO Lisa Su showed off the company’s next big performance game: 3D stacked chiplets, allowing the company to triple the amount of L3 cache on its flagship Zen 3 CPUs.

The technology is exactly what it sounds like: a layer of SRAM cache on top of the Complex Core Die (CCD) of the CPU itself. The current Zen 3 architecture integrates 32 MiB L3 cache per eight-core chiplet, making a total of 64 MiB for a 12- or 16-core chiplet like the Ryzen 9 5900X or 5950X. The new technology adds an additional 64MiB L3 cache on top of each chiplet’s CCD, connected to through-silicon vias (TSVs).

The additional 64MiB L3 cache layer does not extend the width of the CCD, requiring structural silicon to balance the pressure of the CPU cooling system. Compute and cache dies have both been slimmed down in the new design, allowing it to share substrate and heat spreader technology with current Ryzen 5000 processors.

Tripling the L3 cache on Ryzen 5000 provides performance gains under some workloads, especially archive compression/decompression and gaming, similar to that of all-new CPU generations. AMD demonstrated performance improvement via a Gears of War 5 demonstration. Paired with an unspecified GPU and clocked at 4 GHz, a current model 5900X system achieved 184 fps, while the three-cache prototype achieved 206 fps, a gain of about 12 percent.

AMD claims an average of 15 percent improved gaming performance with the new technology, ranging from a low of 4 percent for League of Legends up to a maximum of 25 percent for Monster Hunter: World† This performance boost doesn’t require a smaller process node or higher clock speed – which is especially interesting, in an era where clock speeds have largely hit a wall, and a physics-driven end to process node shrinkage also seems to be on the horizon.

Anandtech’s Ian Cutress notes that AMD’s new 3D chiplet stacking process is clearly TSMC’s SoIC Chip-on-Wafer technology in action. While AMD limits itself – at least so far – to two layers, TSMC has demonstrated a full 12 layers in action. The problem here is thermal – adding RAM is an almost ideal use of the technology, as the extra silicon doesn’t generate much extra heat. Stacking CPU on CPU would be much more problematic.

AMD states that the redesigned 5900X will go into production later this year – well ahead of the planned launch of Zen 4 in 2022. For now, AMD is only focusing on the new technology for “high-end Ryzen” CPUs – no mention was made of it. Epyc, and the extra silicon needed for the added cache makes it likely a no-start for budget processors, given current material shortages.

List image by AMD

Leave a Comment